Investigation on Implementation of Standard Test Access Port and Boundary Scan Architecture at Board and System Levels

标准 测试 存取口与边界扫描结构在印制板级与系统级实现的探讨

In a test situation access to systems might be more relaxed than in a production setting .

在 测试环境下，对系统进行 访问要比在生产设置下更轻松。

Whereas the formal constraint language serve as an effective complement and help testers understand the system test and then further improve the test access rate and coverage rate of test-case .

而形式化约束语言可以对此做到有效补充，它可以帮助测试人员充分理解被测系统，进而提高 测试用例的 获取率以及 测试覆盖率。

Optimizing Test Access Architecture by Genetic Algorithm

用遗传算法优化 测试 通路结构设计

The SoC design methodology introduces new testing challenges and test access becomes a key demand for IP core test reuse .

系统芯片的设计方法为测试技术带来新挑战。知识产权模块（IP核） 测试 访问 机制成为测试复用的关键。

The system uses Visual Basic 6.0 as development platform make full use of VBA and macro technology use Microsoft Access database and its OLE technology in dealing with various types of test data access in order to achieve the operating question of automatic scoring function .

本系统以VISUALBASIC6.0为开发平台，充分利用VBA和宏技术，使用MicrosoftAccess数据库，运用其OLE技术处理 考试中各类数据的 访问，实现了操作题的自动阅卷功能。

In this section of the walkthrough you will add a page to the protected subdirectory and test the access rule .

在演练的此节中，将页添加到受保护的子目录并 测试 访问规则。

The primary reason for cancelling the launch of the revised GRE General Test was test taker access .

取消新GRE考试改革的主要原因是由于新GRE 考试的考点有限， 能够保证参加 考试的考生数量 不足。

A microprocessor based builtin test scheme for SOC is proposed which employs transparency path test access mechanism .

提出了一种基于片上微处理器和透明路径 测试 访问的SOC自测试方案。

With a simple sample application the method was proven to function without any concurrency exceptions using Apache JMeter to test the access .

用一个简单的样例应用程序证明该方法可在没有任何并发性异常的情况下使用ApacheJMeter 测试 存取。

The test for access is done by the cluster service which will have access to a share with the proper permission settings .

访问 测试由群集服务完成，群集 服务有权访问具有适当的权限设置的文件共享。

However with the increase of the number of IP cores in SOC test access of IP cores becomes more difficult . It brings more challenges to SOC test .

然而随着SOC内IP核数目的增多，对IP核的 测试 访问也变得越发困难，这给SOC测试带来了巨大挑战。

However with the increase in the number of IP cores integrated and its function becoming more complex test data volume and test power consumption for SOC grow quickly test access is also more difficult . All the cases pose the more challenges for SOC test .

但随着SOC集成IP核数目的增多，功能越来越复杂，SOC的测试数据量、测试功耗也随之急剧增加，其 测试 访问也变得更加困难，进而也就为SOC的测试带来了更大的挑战。

At last it implements the programming state machine which is to realize Firmware programming in FPGA used VHDL . The state machine successfully produces the test access port scheduling which accords with JTAG protocol interface .

最后，用VHDL语言在FPGA内部实现了对固件编程的编程状态机，该状态机成功的产生了符合JTAG协议接口标准的 测试 端口时序，即固件编程时序。

With the flexible convenient and stable characteristics JTAG ( Joint Test Access Group ) programming tool become widely used in the field of embedded systems .

JTAG（Joint Test AccessGroup）烧写工具具有灵活、方便、稳定等特点，因而在嵌入式系统领域得到了广泛的应用。

In white-box testing the test engineer has access to the internal data structures and algorithms .

在白箱测试中， 测试工程师 能够 访问内部数据结构和算法。

Optimal Test Access Chain Configuration for Reusing NoC to Test IP Cores

复用NoC测试IP芯核 测试 存取链优化配置

Based on the jointed test action group ( JTAG ) protocol instructions and scan chain were introduced . With test access port ( TAP ) module exchanging serial input with parallel output register files and random access memory on chip were read or written in parallel .

在JTAG接口协议的基础上，增加指令和扫描链，同时通过 测试 访问端（TAP）控制把串行输入转换成并行输出，并行访问数字信号处理器的寄存器文件和片上存储器单元，实现嵌入式模拟器。

In a typical SOC test framework to optimize the test wrapper test access mechanism or test scheduling can shorten the testing time for SOCs and solving these problems in conjunction will certainly achieve greater effectiveness .

在目前通用的SOC测试框架中，对测试包封， 测试 访问机制和测试调度进行优化，都能缩短SOC的测试时间。对其三者进行集成优化，能设计出更有效的SOC测试方案。

The test access port and test logic architecture and protocol of 1149.4 and 1149.1 standards are analyzed and behavior models for ABM and DBM are put forward .

文章分析了1149.4和1149.1标准的 测试 访问端口，以及测试逻辑结构和测试协议的异同，提出了模拟边界扫描单元ABM和数字边界扫描单元DBM的行为模型；

In the meantime it also discusses Test Access Machine ( TAM ) for SOC test and the design of JTAG controller .

文中同时还就SOC测试 TAM及JTAG主控制器的设计问题进行了 探讨。

In addition to response time you should test access time-outs and versioning .

除了响应时间，您还应当 测试 访问、超时和版本。

Test Access Mechanism for SOC

SOC 测试 访问机制

SOC test architecture chiefly includes the design of TAM ( Test Access Mechanism ) which is used to transfer test data on chip and the design of chip-level test controller which is used to control the test of the cores on chip .

SOC测试结构主要包括用于传送片上测试数据的 测试 访问机制TAM以及实现对片上核测试控制的芯片级测试控制器设计。

Test Wrapper and Test Access Mechanism Co-optimization for SoC Based on Ant Colony Algorithm

SoC测试 访问机制和 测试壳的蚁群联合优化

The easy JTAG is introduced to control Test Access Port ( TAP ) by computer parallel port .

采用简易JTAG接口，通过计算机并口控制 测试 访问端口。

Test scheduling determines an assignment of cores to test access mechanism such that the overall test application time of system on chip ( SOC ) is minimized .

测试调度是系统芯片测试的一个重要方面，它用于确定把芯片上芯核的测试集分配给 测试 存取机制的方法，以使得总的测试时间最少。

This approach is useful for cloud testing because it addresses the need to test access to an API from multiple access roles or different sets of data ( positive negative boundary values and so on ) .

这种方法对于云测试很有用，因为它解决了 测试从多个访问角色或不同数据集（正、负、边界值，等等） 访问API的需求。

Will the test access raw or routing sockets ?

测试是否将 访问原始或路由套接字？