An algorithm of path based timing optimization by buffer insertion is presented . The algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look up table for gate delay estimation .

提出了一种基于路径的缓冲器插入 时延优化算法，算法采用高阶模型估计连线时延，用基于查表的非线性时延模型估计 门延迟。

Timing driven layout system for gate array and standard cell design & Tiger

时延驱动的 门阵和标准单元布图系统&Tiger

Timer is an important part of Radar system it affords system all the AP timing signals and wave gate timing signals .

定时器是雷达系统的重要部分，它为雷达全机提供所需的各种主 脉冲 定时信号和 波门定时信号。

Clear circuit architecture can be obtained by designing gate class structure describe model and an optimum designing method of a digital circuit system and so is the accurate circuit 's sequence information by timing simulation of describe model of gate class circuit .

门级结构域层次化优化描述模型给出明确的设计电路结构，通过描述模型对 逻辑 门级仿真可得到精确的电路的 时序信息。

The kernel functions such as test signal storage video timing signal generation and systems control signal generation are realized by field programmable gate array ( FPGA ) .

采用现场可编程 门阵列（FPGA）完成测试图案数据存储、各种视频标准 时序产生及系统控制信号产生等核心功能。