Some circuits including the synchronous clock recovery circuit the multiplexing circuit the demultiplexing circuit and the protocol processing circuit are designed .

设计了 同步 时钟恢复电路、复用电路、解复用电路和协议处理电路这四个核心电路。

Synchronous Clock is a key of network synchronization this paper studies system construction key technology based on multimode digital synchronous clock and GPS / GLONASS local clock BPM short wave receiver are used .

同步 时钟是网络同步的关键，本文对基于多模式数字同步时钟产生的系统构成、关键技术、关键技术对系统性能的影响等进行了研究。

Development of a portable synchronous clock with high precision based on GPS and FPGA

基于GPS和FPGA的便携式高精度 同步 时钟的研制

New Method of Generating GPS High Accuracy Synchronous Clock Based on the Digital Phase-lock Principle

基于数字锁相原理的GPS高精度 同步 时钟产生新方法

Designing for High Precision Synchronous Clock Based on GPS-Clock

基于GPS秒时钟的高精度 同步 时钟设计

In order to solve the problem that the optical fiber transmitted phased array radar synchronization signals the method named synchronous clock was designed .

提出了一种 同源 时钟的方法，来解决光纤传输相控阵雷达系统同步信号的问题。

The high-precision clock of DSP is incorporated with the GPS clock to improve the reliability of synchronous clock .

利用DSP的高精度时钟配合同步信号源以提高 同步 时钟的可靠性。

A design of data acquisition system with GPS synchronous clock based on PCI bus is presented .

介绍了一种基于PCI总线、附有GPS 同步 时钟信息的多通道数据采集系统。

Stability study of GPS synchronous clock in the status monitoring system of power network ;

利用 实时 时钟实现的电源管理模块完成节点的工作与 休眠状态功耗控制。

For a long time there is so many technology for the measurement of amplitude and frequency but phase detection technology develops slowly because it is difficult to achieve wide-area precision synchronous clock .

一直以来，对于幅值和频率的测量技术相对很成熟，而相位检测的技术却由于很难达到广域精确 同步 时钟而发展相对迟缓。

The system is pulse-counted by GPS satellite synchronous clock module . DSP reads communication time in real-time in order to control the time precision under microsecond .

系统利用GPS 同步 时钟模块进行脉冲计数，DSP实时读取通信时间，控制时间精度在微秒以下。

Three is to encode data frames avoid long even 0 or even 1 favorable to the long distance transmission of signals and the receiver to extract the synchronous clock .

三是对传输数据帧进行编码，避免长连0或长连1的情况出现，有利于信号的远距离传输和接收端对 同步 时钟的提取。

Design of DPLL for Bit Synchronous Clock Based on FPGA

基于FPGA的提取位 同步 时钟DPLL设计

The IRIG - B decoding device can receive IRIG-B code synchronous clock signals and Pulse Per Second ( PPS ) . The CPLD hardware data acquisition controller ensures the sample time accuracy in the system .

设计了IRIG-B解码器，可以接收IRIG-B 同步 时钟信号和PPS脉冲信号，并且设计了CPLD硬件数据采集控制控制器保证采样的时间精度；

Synchronous clock based on GPS in power system

应用于电力系统中的GPS 同步 时钟

The data transmission through single optical fiber is realized with 16-bits serial output A / D converter and single chip computer . Demodulation of synchronous clock and converting serial to parallel transmission of data are done with CPLD at secondary side .

一次侧利用16位串行A/D结合单片机控制实现了数据的单光纤发送，二次侧的数据接收利用CPLD技术完成 同步 时钟的解调及串行数据的并行转换。

Design and Application of Synchronous Clock Based on GPS Technology

基于GPS技术的 同步 时钟研制及其应用

The GPS synchronous clock and the conversion devices are linked up with RS-485 bus .

本系统主要包括GPS 同步 时钟和通信协议转换模块，二者之间通过RS-485总线进行连接。

According to the system design implementation of various modules is accomplished in the FPGA including decimation polyphase filtering parallel IFFT and synchronous clock management .

根据系统方案，在FPGA内完成了各个功能模块的设计和实现，主要包括：抽取、多相滤波、并行IFFT和 同步 时钟管理。

The synchronous clock of PMU is provided by GPS ( Global Positioning System ) .

PMU的 同步 时钟由全球定位系统GPS（Globalpositioningsystem）提供。

In the way of three pieces of SRAM working in harmony and cooperating with continuous adderss sequence and synchronous clock it outputs a sequence which stimulation and response can switch at any time .

这三片SRAM配合连续地址序列和 同步 时钟的方式，输出一个激励/响应可随时切换的数字激励响应序列。

As technology scales down the design of System-on-Chip encounters some difficult problems : the communication ability can not satisfy the need of system the overall synchronous clock system is difficult to design . That restricts more IP-cores could be integrated on a sigle chip .

随着集成电路制造工艺技术的进步，片上系统SoC在设计过程中遇到了通信能力难以满足系统需求、全局 时钟难以 同步等问题，制约了集成在单一芯片上IP核的规模和数量。

A new GPS Synchronous clock in time servicer

新一代时间服务器&GPS 同步 钟

Development of GPS Based Synchronous Clock and Its Application in Electric Power System

基于GPS的 同步 时钟研制及其在电力系统中的应用

The block transfer mode and synchronous clock are used in its hardware design and the object oriented method and the hierarchical function module management are used in its software design .

文章介绍了系统的构成和特点，在硬件上采用块传输和 同步 时钟等技术，在软件上应用面向对象技术及功能模块分层管理的思想。

Also analyzed several methods about distance measurement and emphasized the distance measurement using synchronous clock .

同时，分析了几种不同的测距方法，并确定了该 同步 钟测距系统的实现方案，对各种不同形式的 同步 钟测距方法进行了详细的论述。

Design of a GPS Synchronous Clock Equipment Based on FPGA

基于FPGA的GPS 同步 时钟装置的设计

This paper details the synchronous clock principle . Also described are the relationship between the noise level and the distance the position of the target ship to the hydrophone and errors of distance measurement .

本文较详细的介绍了 同步 钟测距原理，并对在舰船辐射噪声测量中噪声组与距离关系，目标船相对测量水听器的位置，测距误差等进行了描述。

Research of Multimode Digital Synchronous Clock Technology

多模式数字 同步 时钟产生技术研究