Reduced-complexity timing tracking loop for MC DS-CDMA signals based on vector rotation

基于矢量旋转的MC DS-CDMA信号 定时跟踪方案

Timing Acquisition of Impulse Radio System with Orthogonal Analog Phase Lock Loop

脉冲无线电通信系统的正交锁相 环路 同步方法

The speed signal is an important datum when electric locomotive going it is used by the closed loop timing system of electric locomotive to compose the closed loop control system and it is regarded as the working datum by running monitor recorder in locomotive cab .

速度信号是电力机车运行中的重要数据，电力机车闭环 调速系统要利用速度信号来构成 闭环控制系统，司机控制室的列车运行监控记录装置要以速度信号为工作基准。

To achieve fine symbol timing a loop controlled by numerical controlled oscillator ( NCO ) was used to track the residual timing error and the sampling frequency error after coarse timing acquisition based on a preamble .

基于前导字进行粗同步估计，并采用数字控制振荡器（NCO）控制的 环路对残留符号定时误差和采样频率偏差进行跟踪补偿，以获得精确符号 同步。

Research on Timing Synchronization Algorithm to Burst QPSK Signal Open Loop Structure

开 环结构突发QPSK信号 定时同步算法研究

Application of Reverse Test Method to Avoid Timing Loop

采用反向测试法避免 定时 环路

The loop is a second order phase lock loop consisting of an interpolator a timing error detector and a loop filter .

环路为反馈结构，包括插值器、 时钟误差检测和 环路滤波器三个部分。

Improved all digital timing tracking loop in OFDM systems

OFDM系统中一种改进的全数字 定时跟踪 环

A Novel PN Code Timing Tracking Loop for DS / CDMA Systems

一种改进型PN码 定时跟踪 环

A Method for FSK Timing Recovery Based On Data Transition Tracking Loop

一种基于DTTL 环的FSK 定时 同步方法

The Design of an Interpolation - based Symbol Timing Synchronization Loop

一种基于内插法符号 同步 电路的设计

Also a new scheme of clock timing loop and a new carrier locked detector algorithm are proposed .

主要介绍解调基带部分应用的一些技术和算法，重点对解调器中误差估计的算法进行分析，并提出了1种时钟 定时 环路的实现方案，以及1种载波锁定检测方法。

The structure can overcome the shortcoming of fake timing loop and be used in engineering .

该结构解决了假定 时 环路问题，可应用于工程实际。

The timing recovery in this paper is composed of interpolation timing error detector loop filter and numerically controlled oscillator .

本文设计的定时恢复结构包括插值器、 定时误差检测器、 环路滤波器和数控振荡器四部分。

And the receiver include differential phase discrimination signal detecting frequency estimates and timing tracking loop .

接收机部分包括差分鉴相、匹配滤波、信号检测、 定时 同步、频偏估计和 定时 跟踪等。

The Application of the AC Servo-motor to the Hydraulic Timing Loop

交流伺服电动机在液压 调速 回路中的应用

The injection quantity and the injection timing are controlled on the basis of the MAP and the rail pressure is mainly controlled by using PID of closed loop .

喷油量和喷油 定时通过查MAP图计算来实现，共轨压力则主要采用 闭环PID控制。

In the part of symbol timing recovery interpolation filter timing-error detector loop filter and numerically controlled oscillators are analyzed detailedly . And traditional timing algorithm is improved in timing-error detector .

其中码元 定时恢复部分主要讨论了内插滤波器、定时误差信号的提取、 环路滤波器和数控振荡器的原理和实现方法，并对经典的定时算法进行了必要的改进。

A symbol timing loop for orthogonal frequency division multiplexing ( OFDM ) soft receiver was investigated and a digital interpolation timing loop for OFDM receiver was proposed .

提出了一种可用于正交频分复用（OFDM）软件接收机的全数字化内插同步 环路。

Hardware description language programming constructs ROM RAM memory VGA timing the VGA control Wavelet line transform wavelet transform the IP phase-locked loop seven module in the FPGA hardware platform above .

在FPGA硬件平台上面用硬件描述语言编程构造ROM、RAM存储器、VGA 时序、VGA控制、小波行变换、小波变换、IP锁相 环等七个模块。

Design of Timing Recovery Loop for DVB - C Receiver

DVB-C接收机中的 时钟恢复 电路设计

Algorithms of timing recovery loop and carrier recovery loop employed are analyzed and simulated . Based on this the architecture and hardware implementation schemes of synchronizers of the wideband multi-rate demodulator are proposed .

对 符号 定时恢复 环路、载波恢复环路算法进行了分析和仿真，提出了宽带多速率解调器的总体结构和同步的硬件实现方案。

Then the multi-path capture and the timing acquisition are provided and the critical parameter and the performance of the phase lock loop are discussed .

然后给出了使用正交模拟锁相 环路实现多径捕获和 同步提取的方法和步骤，讨论了锁相 环路的性能和关键参数，给出了在实际信道数据下的模拟结果。

Design the parameter of timing recovery loop . Simulate the convergence of timing recovery loop . And Gardner Timing error correction is used to get timing error information .

设计了 环路各个部分的参数，仿真了 定时恢复算法的收敛情况，证实了Gardner算法在有载波相位误差、交叉串扰情况下仍能够很好收敛。

The loop of this method mainly includes interpolator NCO control timing error test and loop filter resample .

这个系统环路由插值滤波器、gardner 定时误差估计模块、NCO控制器以及 环路滤波器等几个部分组成，文中对各个部分进行了分析并介绍其实现方法。

Then we make some efforts to discuss the timing recovery scheme which is composed of interpolator timing error detector loop filter and numerically controlled oscillator and do the simulation of the scheme .

对于定时恢复的各个部分：内插器、 定时误差检测器、 环路滤波器和数控振荡器进行了详细阐述，并进行了定时环路的仿真。

This paper presents an all digital timing recovery loop in a single chip for DVB-C receiver .

论文提出一种DVB-C基带芯片中全数字 时钟恢复 电路的解决方案。

By adopting code rate as timing benchmark the code tracking loop in the receiver tracks and calculates the sampling frequency offset between the actual and nominal values .

接收机的码跟踪 环路以码速作为 时间基准，对采样频率实际值与标称值之间的偏差进行跟踪，环路 稳定后得到该偏差的估计值，其采样频率的准确度可提高到10-7量级。

Implementation of autocontrol technology with frequency conversion and timing by dint of single dragging two and closed loop

一拖二 闭环变频 调速自动控制技术的实施