Research on Formal Verification Method for VLSI Design

VLSI设计中的形式验证方法研究

VLSI decoding design of low-density parity-check codes based on circulant matrices

基于循环矩阵的低密度校验码的 VLSI译码设计

Design and Implementation of VLSI Architecture for Lifting-based Discrete Wavelet Transform

基于提升的离散小波变换 VLSI结构设计与实现

VLSI Design of an Efficient Reconfigurable FFT Processor and its Application

高效可配置FFT处理器的 VLSI设计及其应用

Current-mode filters have been paid more attention for their high speed lower power consumption wider dynamic range and compatibility with VLSI technology .

电流模式滤波器由于具有高速、低功耗、动态范围大、且与 VLSI技术兼容的特点，引起了滤波器研究领域的极大关注。

With the rapid development of nanometer technology the design of VLSI meets a great deal challenge .

纳米技术的飞速发展对超大规模集成电路（ VLSI）设计技术提出了越来越大的挑战。

This article has studied the function verification method which in the traditional VLSI design uses has analyzed each method characteristic and the deficiency .

本文在研究了传统的 VLSI设计中采用的功能验证方法后，分析了各种方法的特点和不足之处。

Research on Interconnection Crosstalk Noise for VLSI Design

VLSI设计中的互连串扰噪声研究

By adopting optimal demodulation algorithm and optimizing VLSI implementation architecture this demodulator achieves high performance at low hardware costs .

通过采用改进的解调算法并优化其 VLSI实现结构，该设计在现场测试中不仅取得良好的性能并且节约了硬件资源。

Low-cost and Reconfigurable VLSI Implementation of Channel Estimation for DTMB System

低成本可配置DTMB系统信道估计的 VLSI实现

An Architecture and VLSI Implementation for Adaptive Reed-Solomon Decoder

一种高速自适应Reed-Solomon译码结构及其 VLSI优化实现

Through the research of VLSI architecture of fast codewords search algorithms we can provide a foundation for the implementation of detailed and sophisticated image coding schemes in the future .

通过对矢量量化快速码字搜索算法的 VLSI结构的研究，为进一步设计更为详细和复杂的图象编码系统提供基础。

Very large-scale integration ( VLSI ) vastly increased circuit density giving RisE to the microprocessor .

大规模集成 电路更大的增加了微处理器的电路密度。

VLSI Design of Reconfigurable SRRC Filter and Its Automatic Code Generation

一种参数可配置的SRRC滤波器的 结构设计及其代码的自动生成方法

VLSI Design and Implementation of Motion Compensation for MPEG-4 Decoder

MPEG-4解码器的运动补偿 VLSI设计与实现

Design of AES VLSI in wireless sensor networks

无线网络化传感器中的AES VLSI设计

A gridless routing algorithm for VLSI design is presented in this paper .

本文提出一种高性能 超大 规模 集成 电路无网格布线算法。

A Method of Timing Closure Based on OCV in the VLSI Design

超大 规模 集成 电路中基于OCV的时序收敛方法

In this dissertation the VLSI ( very large scale integration ) test method based on IDDT ( transient current ) information a new hot spot of test strategies is researched .

本文对作为新的研究热点的测试方法&基于动态电流测试信息的 VLSI测试方法进行了研究。

Lifetime Modeling and Characteristics of TDDB in VLSI Copper Interconnection

VLSI铜互连可靠性TDDB特性及其寿命评估模型研究

The VLSI Design of Linear Convolution Based on CRT and CSD Multiplication

基于中国余数定理和 CSD乘法的线性卷积设计

With the development of VLSI and semiconductor manufacture technics SoC ( Syctem on a Chip ) is applied to various fields more and more widely .

随着 大规模 集成 电路和半导体工艺的发展，片上系统越来越广泛地被应用到各个领域。

For example one of the constraints in VLSI routing problems is minimizing wire length .

比如，在超大规模集成电路（ VLSI）布线问题中的一个约束条件就是要使线路最短。

Research on VLSI Net Routing Based on Tabu-ant Colonies System

基于禁忌蚁群系统的 VLSI线网布线研究

Research on Testability and Low Power Design Method in VLSI High-Level Synthesis

VLSI高层次综合中可测性和低功耗设计方法研究

Research and Design of Motion Estimation Hardware Architecture for VLSI

基于 VLSI的运动估计算法结构的研究和设计

Low power design is playing a more and more important role in VLSI nowadays .

低功耗设计在当前 超大 规模 集成 电路中越来越重要。

A self-test scheme under which all test patterns for adder under test in VLSI are produced by the adder self is presented based on arithmetic additive generator .

基于算术加法测试生成，提出了 VLSI中加法器的一种自测试方案：加法器产生自身所需的所有测试矢量。

Macro-model of VLSI Partial Power Networks

VLSI局部电源网络的宏模型研究

The characteristic model of interconnects in VLSI is proposed .

本文提出了 大规模 集成 电路中互连线的特征模型。